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| INTEGRATED CIRCUITS DATA SHEET PNX3000 Analog front end for digital video processors Preliminary specification Supersedes data of 2004 Jun 24 2004 Oct 04 Philips Semiconductors Preliminary specification Analog front end for digital video processors CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 8 8.1 8.2 FEATURES GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Vision IF DTV IF Sound IF CVBS/YC source selector RGB/YPbPr source selector Video ADCs and anti-alias filters Audio source selectors and A to D converters Microphone inputs Clock generation, timing circuitry and black level clamping Data link transmitters I2C-bus transceiver Power supply circuit East-west interface I2C-BUS SPECIFICATION Input control registers Output status registers 9 10 11 11.1 12 13 13.1 13.2 14 15 15.1 15.2 15.3 15.4 15.5 16 17 18 19 LIMITING VALUES PNX3000 THERMAL CHARACTERISTICS QUALITY SPECIFICATION Latch-up performance CHARACTERISTICS TEST AND APPLICATION INFORMATION Power supply decoupling Application diagram PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS PURCHASE OF PHILIPS I2C COMPONENTS 2004 Oct 04 2 Philips Semiconductors Preliminary specification Analog front end for digital video processors 1 FEATURES PNX3000 * Multi-standard vision IF circuit with alignment-free PLL demodulator without external components * Internal (switchable) time-constant for the IF AGC circuit * DTV IF circuit for gain control of digital broadcast TV signals * Sound IF amplifier with separate AGC circuit for quasi-split sound * IF circuit can also be used for intercarrier sound * Analog demodulator for AM sound * Integrated sound trap and group delay correction * Video ident function detects the presence of a video signal * Video source selector with four external CVBS or YC inputs and two analog CVBS outputs with independent source selection for each output * Two linear inputs for 1fH or 2fH RGB signals with source selector; the RGB signals are converted to YUV before A to D conversion; both inputs can also be used as YPbPr input for DVD or set top box * Integrated anti-alias filters for video Analog to Digital Converters (ADCs) * Four 10-bit video ADCs for the conversion of CVBS, YC, YUV and down-mixed sound IF signals * Up to three different A to D converted video channels are available simultaneously (e.g. CVBS, YC and YUV) * Audio source selector with five stereo inputs for analog audio and two microphone inputs 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PNX3000HL/N3 LQFP128 DESCRIPTION plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm VERSION SOT425-1 * Two microphone amplifiers with adjustable gain * Three analog audio outputs for SCART and line out with independent source selection for each output * Four 1-bit audio sigma delta ADCs for the conversion of audio and microphone signals * Three serial data link transmitters for interfacing with the digital video processor at a bit rate of 594 Mbit/s per data link * Voltage to current converter for driving external east-west power amplifier * I2C-bus transceiver with selectable slave address and maskable interrupt output. 2 GENERAL DESCRIPTION The PNX3000 is an analog front end for digital video processors. It contains an IF circuit for both analog and digital broadcast signals, input selectors and ADCs for analog video and audio signals. The digital output signals are made available via three serial data links. The IC has a supply voltage of 5 V. The supply voltage of the analog audio part can be 5 V or 8 V, depending on the maximum signal amplitudes that are required. 2004 Oct 04 3 Philips Semiconductors Preliminary specification Analog front end for digital video processors 4 QUICK REFERENCE DATA SYMBOL Supply VP IP ICC(ASW) Input signals Vi(VIF)(dif)(rms) Vi(DTVIF)(dif)(rms) Vi(SIF)(rms) Vi(CVBS/Y)(p-p) Vi(RGB)(b-w) Vi(Y)(p-p) Vi(Pb)(p-p) Vi(Pr)(p-p) Video ADCs Bv(-3dB) fsample RES -3 dB signal bandwidth sample frequency resolution 1fH mode 1fH mode - - - - 0 9 27 10 video IF amplifier sensitivity (differential; RMS value) video DTV IF amplifier sensitivity (differential; RMS value) sound IF amplifier sensitivity (RMS value) CVBS or Y input voltage (peak-to-peak value) RGB inputs (black-to-white value) luminance input signal (peak-to-peak value) Pb input signal (peak-to-peak value) Pr input signal (peak-to-peak value) note 2 note 2 note 2 note 2 -3 dB - - - - - - - - 75 75 45 1.0 0.7 1.0 0.7 0.7 main supply voltage main supply current note 1 note 1 audio supply current 4.75 - 4.75 - 5.0 285 8.0 3.5 PARAMETER CONDITIONS MIN. TYP. PNX3000 MAX. UNIT 5.25 320 8.4 5.0 V mA V mA V V dBV V V V V V VCC(1ASW), VCC(2ASW) audio supply voltage 150 150 tbf 1.76 1.0 1.43 1.0 1.0 - - - - 1 MHz MHz bit Analog output signals Vo(CVBS)(p-p) Io(TUNERAGC) Notes 1. The supply voltage for the analog audio part of the IC can be 5 V or 8 V. For a supply voltage of 5 V the maximum signal amplitudes at in- and outputs are 1 V (RMS). For a supply voltage of 8 V the maximum amplitudes are 2 V (RMS). 2. The RGB inputs can also be used as YPbPr input. The selection is made via the I2C-bus. The YPbPr input sensitivity is in accordance with the DVD player specification. analog CVBS output voltage (peak-to-peak value) tuner AGC output current range 2.0 - V mA 2004 Oct 04 4 Philips Semiconductors Preliminary specification Analog front end for digital video processors 5 BLOCK DIAGRAM 1x CVBSOUTA CVBSOUTB 2NDSIFEXT (FMRAD) SIFAGC CVBSOUTIF PNX3000 handbook, full pagewidth SIFIN 2 SIF AMP QSS MIXER & AM SND DEMOD Fpc 2nd SIF internal DTV 1st IF SWITCH 2 DTVOUT VIFIN DTVIFIN DTVIFAGC TUNERAGC DTVIFPLL VIFPLL CVBS0 CVBS1 CVBS2 CVBS/Y3 C3 CVBS/Y4 C4 YCOMB CCOMB CVBS_DTV 2 2 IF SWITCH 2 VIF AMP VIF PLL & DTVIF MIXER DTV 2nd IF SNDTRAP & GROUP DELAY PNX3000 CVBS_IF CVBS/Y_PRIM CVBS PRIM. SWITCH A C VIDEO IDENT ICLP CLP_PRIM 2ndSIF AGC DET CVBS OUT SWITCH & CVBS SEC. SWITCH CLP_SEC CLP_YUV ICLP A Yyuv RGB/YUV MATRIX & SWITCH U L1/AMint A D R1/AMext A D L2/MIC1/PipMono MIC AMPS A D R2/MIC2/AM A D MIC1 AM int AUDIO SWITCH (DIGITAL OUT) MIC2 6.75 MHz ADC CLOCK PLL DIVIDER XREF 13.5 or 27 MHz R L 2 R 2 L V A D CLK BAND GAP REF DATALINK PLL 27 MHz 13.5 MHz 54 MHz D CLK 10 VDEFLO VDEFLS VAUDO VAUDS RREF VD2V5 VAUD VDEFL ICLP 10 DATA LINK 2 4 DLINK2 2NDSIFAGC D CLK 297 MHz 10 DATA LINK 1 4 DLINK1 AM sound VCA A CVBS_SEC D CLK ICLP 10 DATA LINK 3 4 DLINK3 297 MHz R1/PR1/V1 G1/Y1/Y1 B1/PB1/U1 R2/PR2/V2 G2/Y2/Y2 B2/PB2/U2 297 MHz BGDEC primary digital audio secondary digital audio 297 MHz MIC1 2 MIC2 2 AUDIO SWITCH (ANALOG OUT) CLP_PRIM CLP_YUV AUDIO AMPS CLP_SEC TIMING CIRCUIT HV_PRIM HV_SEC VOLTAGE TO CURRENT I2C-BUS INTERFACE IRQ MCE430 R1 R2 R3 R4 R5 L1 L2 L3 L4 L5 AM EXT REW DSNDL1 LINEL SCART2R ADR SCL SDA LINER SCART2L DSNDR1 DSNDL2 SCART1L DSNDR2 EWVIN SCART1R EWIOUT Fig.1 Block diagram. 2004 Oct 04 5 Philips Semiconductors Preliminary specification Analog front end for digital video processors 6 PINNING SYMBOL CVBS2 VAUDO VAUDS CVBS/Y3 C3 GND(VSW) BGDEC CVBS/Y4 C4 FUSE GND(FILT) CVBS_DTV RREF VCC(FILT) YCOMB CCOMB AMEXT TESTPIN3 CVBSOUTA VDEFLO VDEFLS CVBSOUTB FUSE TESTPIN2 R1/PR1/V1 G1/Y1/Y1 B1/PB1/U1 VCC(RGB) GND(RGB) R2/PR2/V2 G2/Y2/Y2 B2/PB2/U2 FUSE GND(VADC) VCC(VADC) EWVIN EWIOUT REW ADR XREF 2004 Oct 04 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 CVBS2 input DC output voltage for supply of audio DACs in digital decoder sense voltage input for audio DACs supply external CVBS/Y3 input external CHROMA3 input ground video switch bandgap decoupling external CVBS/Y4 input external CHROMA4 input fused lead ground filters input for CVBS encoded signal from DTV decoder reference current input supply voltage filters (5 V) Y signal input from 3D Comb filter C signal input from 3D Comb filter external AM mono input test pin 3; must be left open CVBS or Y+CHROMA output A DESCRIPTION PNX3000 DC output voltage for supply of deflection DACs in digital decoder sense input voltage for deflection DACs supply CVBS or Y+CHROMA output B fused lead test pin 2; connect to ground R input 1 of RGB signal Pr input 1 of YPbPr signal or V input 1 of YUV signal G input 1 of RGB signal or Y input 1 of YPbPr signal or Y input 1 of YUV signal B input 1 of RGB signal Pb input 1 of YPbPr signal or U input 1 of YUV signal supply voltage RGB matrix (5 V) ground RGB matrix R input 2 of RGB signal Pr input 2 of YPbPr signal or V input 2 of YUV signal G input 2 of RGB signal or Y input 2 of YPbPr signal or Y input 2 of YUV signal B input 2 of RGB signal Pb input 2 of YPbPr signal or U input 2 of YUV signal fused lead ground video ADCs supply voltage video ADCs (5 V) east-west input voltage east-west output current east-west voltage to current conversion resistor I2C-bus address selection input XTAL reference frequency input 6 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL FUSE IRQ SDA SCL HV_SEC HV_PRIM VD2V5 GND(DIG) VCC(DIG) STROBE3N STROBE3P DATA3N DATA3P FUSE STROBE2N STROBE2P DATA2N DATA2P GND(I2D) STROBE1N STROBE1P DATA1N DATA1P VCC(I2D) SCART2R SCART2L LINER LINEL SCART1R SCART1L FUSE DSNDR2 DSNDL2 DSNDR1 DSNDL1 GND(AADC) VCC(AADC) FUSE R4 L4 R3 2004 Oct 04 PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 fused lead interrupt request output I2C-bus serial data input and output I2C-bus serial clock input horizontal and vertical sync input for secondary video channel horizontal and vertical sync input for primary video channel decoupling of internal digital supply voltage digital ground digital supply voltage (5 V) strobe negative data link 3 strobe positive data link 3 data negative data link 3 data positive data link 3 fused lead strobe negative data link 2 strobe positive data link 2 data negative data link 2 data positive data link 2 ground data links strobe negative data link 1 strobe positive data link 1 data negative data link 1 data positive data link 1 supply voltage data links (5 V) audio output for SCART2 right audio output for SCART2 left audio line output right audio line output left audio output for SCART1 right audio output for SCART1 left fused lead audio signal input from digital decoder right 2 audio signal input from digital decoder left 2 audio signal input from digital decoder right 1 audio signal input from digital decoder left 1 ground audio ADCs supply voltage audio ADCs (5 V) fused lead right input audio 4 left input audio 4 right input audio 3 7 DESCRIPTION PNX3000 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL L3 R2 L2 R1 L1 GND(2ASW) VCC(2ASW) VAADCREF VAADCN VAADCP MIC2N MIC2P MIC1N MIC1P FUSE GND(1ASW) VCC(1ASW) SIFINP SIFINN SIFAGC DTVIFAGC DTVIFINP DTVIFINN TUNERAGC FUSE VIFINP VIFINN DTVIFPLL VCC(IF) VIFPLL GND(1IF) 2NDSIFEXT 2NDSIFAGC GND(2IF) DTVOUTP DTVOUTN VCC(SUP) FUSE CVBSOUTIF GND(SUP) VCC(1VSW) 2004 Oct 04 PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 left input audio 3 right input audio 2 left input audio 2 right input audio 1 left input audio 1 ground 2 audio switch supply voltage 2 audio switch (audio output buffers; 5 or 8 V) decoupling of reference voltage for audio ADCs 0 V reference voltage for audio ADCs (GND) full scale reference voltage for audio ADCs (5 V) microphone input 2, negative microphone input 2, positive microphone input 1, negative microphone input 1, positive fused lead ground 1 audio switch supply voltage 1 audio switch (audio input buffers; 5 or 8 V) sound IF input, positive sound IF input, negative control voltage for sound IF AGC control voltage for DTV IF AGC DTV IF input, positive DTV IF input, negative tuner AGC output fused lead vision IF input, positive vision IF input, negative output loop filter DTV IF PLL demodulator supply voltage IF circuit (5 V) output loop filter VIF PLL demodulator ground 1 IF circuit second sound IF input second sound IF AGC capacitor ground 2 IF circuit DTV output, positive DTV output, negative supply voltage of supply circuit (5 V) fused lead CVBS output of IF circuit ground of supply circuit supply voltage 1 of video switch (5 V) 8 DESCRIPTION PNX3000 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL CVBS0 TESTPIN1 VCC(2VSW) CVBS1 R5 L5 PIN 123 124 125 126 127 128 test pin 1; connect to ground supply voltage 2 of video switch (5 V) CVBS1 input right input audio 5 left input audio 5 DESCRIPTION CVBS0 input for CVBS from IF part PNX3000 2004 Oct 04 9 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 120 CVBSOUTIF 114 2NDSIFAGC 125 VCC(2VSW) 124 TESTPIN1 122 VCC(1VSW) 113 2NDSIFEXT 121 GND(SUP) 118 VCC(SUP) 117 DTVOUTN 116 DTVOUTP handbook, full pagewidth 105 TUNERAGC 109 DTVIFPLL 104 DTVIFINN CVBS2 VAUDO VAUDS CVBS/Y3 C3 GND(VSW) BGDEC CVBS/Y4 C4 1 2 3 4 5 6 7 8 9 103 DTVIFINP 102 DTVIFAGC 101 SIFAGC 100 SIFINN 99 SIFINP 98 VCC(1ASW) 97 GND(1ASW) 96 FUSE 95 MIC1P 94 MIC1N 93 MIC2P 92 MIC2N 91 VAADCP 90 VAADCN 89 VAADCREF 88 VCC(2ASW) 87 GND(2ASW) 86 L1 85 R1 84 L2 83 R2 82 L3 81 R3 80 L4 79 R4 78 FUSE 77 VCC(AADC) 76 GND(AADC) 75 DSNDL1 74 DSNDR1 73 DSNDL2 72 DSNDR2 71 FUSE 70 SCART1L 69 SCART1R 68 LINEL 67 LINER 66 SCART2L 65 SCART2R VCC(I2D) 64 MCE429 115 GND(2IF) 112 GND(1IF) 110 VCC(IF) 111 VIFPLL 126 CVBS1 123 CVBS0 108 VIFINN GND(I2D) 59 107 VIFINP STROBE1N 60 119 FUSE FUSE 10 GND(FILT) 11 CVBS_DTV 12 RREF 13 VCC(FILT) 14 YCOMB 15 CCOMB 16 AMEXT 17 TESTPIN3 18 CVBSOUTA 19 VDEFLO 20 VDEFLS 21 CVBSOUTB 22 FUSE 23 TESTPIN2 24 R1/PR1/V1 25 G1/Y1/Y1 26 B1/PB1/U1 27 VCC(RGB) 28 GND(RGB) 29 R2/PR2/V2 30 G2/Y2/Y2 31 B2/PB2/U2 32 FUSE 33 GND(VADC) 34 VCC(VADC) 35 EWVIN 36 EWIOUT 37 REW 38 ADR 39 XREF 40 FUSE 41 IRQ 42 SDA 43 SCL 44 HV_SEC 45 HV_PRIM 46 VD2V5 47 GND(DIG) 48 VCC(DIG) 49 STROBE3N 50 STROBE3P 51 DATA3N 52 DATA3P 53 FUSE 54 STROBE2N 55 STROBE2P 56 DATA2N 57 DATA2P 58 STROBE1P 61 DATA1N 62 DATA1P 63 PNX3000HL Fig.2 Pinning configuration. 2004 Oct 04 10 106 FUSE 127 R5 128 L5 Philips Semiconductors Preliminary specification Analog front end for digital video processors 7 7.1 FUNCTIONAL DESCRIPTION Vision IF PNX3000 that is approximately 4 MHz higher than the incoming 1st IF centre frequency. In DTV 2nd IF mode the 2nd IF signal is obtained by down-mixing the incoming DTV IF signal with the IF VCO signal. The low-pass filtered DTV 2nd IF signal is available as a differential signal at the DTV output. This signal may have a maximum bandwidth of 10 MHz. The VCO frequency is programmed via the I2C-bus in steps of 250 kHz. In DTV mode the AGC time constant is determined by a capacitor on pin DTVIFAGC. There are two AGC modes: internal and external. In the internal AGC mode the gain is controlled by an internal AGC detector. The external AGC mode is activated by bit AGCM. In this mode the appropriate AGC pin is used as input, so that the IF gain can be controlled by the DTV channel decoder. The IF PLL has two pins for connection of the PLL loop filters, one for analog TV and one for DTV. This allows each loop filter to be optimized for its application. 7.3 Sound IF The IF amplifier contains 3 AC-coupled control stages which have a total gain control range of more than 66 dB. The video signal is demodulated by means of an alignment-free PLL carrier regenerator with an internal VCO. This VCO is calibrated by means of a digital control circuit which uses the external crystal frequency as a reference. The frequency setting for the various standards (33.4 MHz, 33.9 MHz, 38 MHz, 38.9 MHz, 45.75 MHz and 58.75 MHz) is realised via the I2C-bus. To improve performance for phase modulated carrier signals the control speed of the PLL can be increased by setting bit FFI. The AFC output is generated by the digital control circuit of the IF PLL demodulator and can be read via the I2C-bus. For fast search tuning systems the window of the AFC can be increased with a factor of three with bus bit AFW. The AGC-detector operates on top sync or top white level. The demodulation polarity is switched via the I2C-bus. The AGC detector capacitor is integrated. The time-constant can be chosen via I2C-bus bits AGC1 and AGC0. The AGC has also an external mode which is activated by bit AGCM. In this mode the IF gain is determined by an external voltage on pin DTVIFAGC. The IC has an integrated sound trap filter. The filter is constructed as a cascade of three separate traps, to realize sufficient suppression of the first and second sound carriers. The trap frequencies are selected via the I2C-bus. The IC has an integrated group delay correction filter. The filter can be switched between the PAL BG curve and a flat group delay response characteristic. This has the advantage that in multi-standard receivers the video SAW filter does not need to be switchable. 7.2 DTV IF The PNX3000 has a separate sound IF input to enable quasi-split sound applications. The sound IF amplifier is similar to the vision IF amplifier and has a gain control range of about 55 dB. The AGC detector measures the average level of the AM or FM SIF carrier and ensures a constant signal amplitude for the AM demodulator and Quasi-Split Sound (QSS) mixer. The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to the intercarrier frequency by mixing it with the regenerated picture carrier from the video IF VCO. With this system a high performance stereo sound processing can be achieved. For applications without a SIF SAW filter the IC can also be used in intercarrier mode. In this mode the composite video signal from the VIF amplifier is fed to the QSS mixer and converted to the intercarrier frequency. AM sound demodulation is realised in the analog domain by the QSS mixer. The modulated SIF signal is multiplied in phase with the limited SIF signal. The demodulator output signal is low-pass filtered for suppression of the carrier harmonics. The demodulated AM signal can be digitized by one of the audio ADCs. The QSS mixer can also be used for down-mixing an FM radio IF signal to an intercarrier frequency, so that it can be demodulated by the digital decoder. The IF PLL must be set to synthesizer mode in this case. The preferred solution is to supply the FM radio signal via a 11 Apart from processing analog TV signals, the IF circuit can also be used to preprocess digital TV signals before they are sent to a DTV channel decoder. For this application the two modes of operation are DTV 1st IF and DTV 2nd IF. For both operating modes the IF PLL must be set to synthesizer mode. In DTV 1st IF mode only the AGC function of the IF circuit is used, so the DTV channel decoder must be able to handle the 1st IF frequency. Because the AGC detector operates on the down-mixed 2nd IF signal, it is still important to program a valid frequency for the IF VCO. It is recommended to set the frequency of the VCO to a value 2004 Oct 04 Philips Semiconductors Preliminary specification Analog front end for digital video processors separate SAW or ceramic filter to the DTV input of the PNX3000. The reason is that the selectivity of a SAW filter for TV sound is not sufficient for FM radio and, if the SIF input is used, no tuner AGC information is available. For high performance FM radio it is recommended that a 10.7 MHz FM radio IF signal is supplied to the external 2nd SIF input. In this case the IF signal must be filtered by an external bandpass filter, that also functions as an anti-alias filter. The low-pass filter before the 2nd SIF ADC must be bypassed by setting bus bit SLPM. The IC includes a separate AGC circuit for the 2nd SIF signal. This AGC is needed for intercarrier sound applications and when an external sound IF signal is supplied to the 2nd SIF input. The AGC amplifier is preceded by a second order high-pass filter for suppression of video signal components. The AGC time constant is determined by an external capacitor. 7.4 CVBS/YC source selector 7.5 RGB/YPbPr source selector PNX3000 The IC has two RGB inputs. Both inputs can also be used as YPbPr input for connecting video sources with an YPbPr output like a DVD player. The RGB inputs can also be used for fast insertion of RGB signals (for instance on screen display menus) in the primary CVBS signal. The fast insertion switch is located in the digital video processor. The RGB signals are converted to YUV before further processing. The YUV output signal is digitized by two ADCs. The U and V components have half the bandwidth of the Y signal, therefore the U and V signals are multiplexed and digitized by one ADC. 7.6 Video ADCs and anti-alias filters The video input selector consists of four independent source selectors, that can select between the CVBS signal coming from the IF part and four external CVBS signals. Two of the external CVBS inputs can also be used as YC input. One selector is used to select the signal for of the primary video channel. A second selector selects the CVBS or YC signal for the secondary channel. The third and fourth selectors are used to select analog outputs CVBS A and B, which can be used for SCART or line output. The primary channel can be a CVBS or YC signal. If a YC signal is selected for the secondary channel or for the external CVBS outputs A or B, the luminance and chrominance signals are added to obtain a CVBS signal. The IC has an extra YC input for connection of a 3D comb filter. The comb signal can only be selected for the primary video channel. The input pin CVBS_DTV allows an analog CVBS signal derived from a digital broadcast (MPEG) signal to be recorded with an analog VCR. This signal cannot be selected for the primary video channel. The video identification circuit detects the presence of a video signal on the CVBS_IF input (pin CVBS0). The identification output is normally used to detect transmitters during search tuning and can be read via the I2C-bus. The circuit can also be used to monitor the selected primary CVBS or YC signal. Either mode is selected by bit VIM. The PNX3000 contains four video ADCs for analog and digital video broadcast signals. The clock frequency for the ADCs is either 27 MHz or 54 MHz. Two analog signals can be multiplexed at the input of one ADC. Then the clock frequency of the ADC is 54 MHz and the sample frequency of each channel is 27 MHz. The video ADCs are 10-bit folding ADCs. The sample frequency for standard 1fH video signals is 27 MHz. For the YUV channel the sample frequency of the U and V components is half the sample frequency of the Y signal. For 2fH YPbPr or RGB input signals (for instance 480p or 1080i ATSC signals), the frequency that is used to sample the YUV signals is twice as high as for 1fH signals. The sample frequency is 54 MHz for Y and 27 MHz for U and V. The high sample frequency requires two data links to transport the video data to the digital video processor. The anti-alias filters before the ADCs limit the signal bandwidth to prevent aliasing effects. The filters for YUV can be bypassed by means of two separate bits: bit BPY for the Y filter and bit BPUV for the U and V filters. This enables the use of external anti-alias filters with increased bandwidth for 2fH, RGB or YPbPr input signals. Table 1 shows the signal bandwidths and sample rates for the various types of video signals. Table 2 shows which video signals are sent to the digital video processor for both data link modes. 2004 Oct 04 12 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 1 Overview of anti-alias filter bandwidths and video signal sample rates. SIGNAL COMPONENT Y C YUV 1fH Y U V YUV 2fH Y U V DTV 2nd SIF 7.7 - - SIGNAL BAND -1.0 dB (MHz) 8 8 8 8 4 4 16 8 8 10 8 7.8 SIGNAL BAND -3.0 dB (MHz) 9 9 9 9 4.5 4.5 18 9 9 12 9 Microphone inputs PNX3000 SIGNAL TYPE CVBS YC SAMPLE FREQUENCY (MHz) 27 27 27 27 13.5 13.5 54 27 27 - 27 Audio source selectors and A to D converters The PNX3000 contains two different audio source selectors. The first selector selects which audio signals are routed to the audio ADCs for further processing in the digital domain. The two microphone inputs are also connected to this selector. The selector has two outputs, a primary channel and a secondary channel. The primary audio channel is used for one stereo signal. The secondary audio channel can carry a second stereo signal, or two microphone signals, or one mono signal and one microphone signal or one mono signal and one AM sound signal. The second selector selects which audio signals are fed to the analog audio outputs for SCART and line out. This selector also has two stereo inputs for demodulated sound signals coming from the digital video processor. The gain from an external audio input to an analog output is 1. A supply voltage of 5 V allows input and output amplitudes of 1 V (RMS) full scale. The PNX3000 has separate supply voltage pins for the audio selector circuit. To allow for input and output amplitudes of 2 V (RMS) full scale, as required for compliance with the SCART specification, an audio supply voltage of 8 V must be used. The audio ADCs are 1-bit sigma-delta converters that operate at a clock frequency of 6.75 MHz. The audio A to D clock is synchronous with the video A to D clock, so that audio and video data can be sent over the same data links. The effective audio sample rate is f clk --------- = 52.7 ksample/s. 128 The IC has two microphone inputs. One microphone input can be used for voice control of the TV set with the help of an intelligent voice command decoder. The second input can be used for connection of a microphone for Karaoke. To allow the use of microphones with different sensitivities the gain of each microphone amplifier is switchable between two values via the I2C-bus. 7.9 Clock generation, timing circuitry and black level clamping The IC contains two PLL circuits that derive the sample clock for the ADCs and the bit and word clocks for the data links from an external reference frequency. The reference frequency must be a stable frequency of either 13.5 MHz or 27 MHz from a crystal oscillator. The internal reference frequency is always 13.5 MHz. If the external frequency is 27 MHz a prescaler must be activated by bus bit FXT. One PLL is used to multiply the 13.5 MHz reference frequency to the 27 MHz and 54 MHz clock frequencies that are needed for the video ADCs. A second PLL is used to obtain the 297 MHz bit clock for the data link transmitters. A special timing circuit is used to generate the horizontal and vertical timing pulses that are needed in the IF part, and also for clamping the black level of the selected video signals to a defined value at the output of the video ADCs. The horizontal and vertical timing information of the primary and secondary video channels must be supplied by the digital video processor on pins HV_PRIM and HV_SEC. The signal on these pins must consist of a 2004 Oct 04 13 Philips Semiconductors Preliminary specification Analog front end for digital video processors horizontal timing pulse that starts just before and ends just after the horizontal sync pulse of the selected video signal. To enable detection of the vertical blanking period, the horizontal pulses must be wider during a number of lines in the vertical blanking interval. The clamp signal inside the IC is generated with the help of the external horizontal timing pulse and the 13.5 MHz clock. The vertical timing information is used to disable the black level clamp, so that the black level is not disturbed by the vertical sync pulse on the video signal. The clamp pulse for the YUV channel can be derived from the primary or the secondary HV pulse, and is selected by bus bit CLPS. To avoid signal disturbance, it is possible to disable the black clamps when the horizontal PLL in the digital video processor is not locked to the selected video signal. This is done by bus bit CMP for the primary CVBS channel and bus bit CMS for the secondary CVBS channel. Special attention is required when the same CVBS input is selected for primary and secondary CVBS channels. In this case the black level clamp loop is only closed for the primary CVBS input. Due to internal offsets this will normally result in a deviation on the black level of the digitized secondary CVBS output. 7.10 Data link transmitters PNX3000 Table 2 shows which video signals are sent to the digital video processor for both data link modes. In the standard mode up to three video channels plus one sound IF signal are digitized and transferred simultaneously over the data links. The distance between both ICs that are connected via the data link must not be larger than about 10 centimetres. The two wires for each differential signal should be paired in the layout of the printed-circuit board. 7.11 I2C-bus transceiver The slave address of the I2C-bus transceiver in the PNX3000 has two possible values, selected via the ADR pin. The maximum bus clock frequency is 400 kHz, and the voltage swing of SCL and SDA can be 3.3 V or 5 V. The I2C-bus transceiver also has a hardwired IRQ output (open drain and LOW-active) for interruption of the microprocessor when the value of an important status bit in status byte 0 changes. The IRQ signal is maskable with register 0FH. 7.12 Power supply circuit Three serial data links are used for transportation of the digital video and audio data coming from the ADCs in the PNX3000 to the digital video processor. The use of serial data connections results in a considerable reduction in pin count and the number of connection wires that are needed between both ICs. The communication between data link transmitter and data link receiver consists of two signals, a data signal and a strobe signal. The two signals together contain the data, bit-sync and word-sync information. For optimal EMC performance both data and strobe are low voltage differential signals. The voltage swing on each wire is 300 mV. Each data word sent over a data link consists of 44 bits: 4 video samples of 10 bits each, 2 audio bits and 2 word-sync bits. The word clock is 13.5 MHz. The data rate on each of the three data links is 594 Mbit/s. An internal bandgap circuit generates a stable voltage of 1.25 V. This voltage is multiplied to a reference voltage of 2.3 V, and a digital supply voltage of 2.5 V. These two voltages must be decoupled by external capacitors. A 1/2VP reference voltage for the audio ADCs also requires an external decoupling capacitor. The PNX3000 contains two voltage regulators to supply the SDACs that are used in the digital video processor. Each regulator requires a few external components (one transistor, two resistors and a decoupling capacitor). The output voltage is adjustable between 1.25 V and 3.3 V by selection of external resistors values. 7.13 East-west interface The PNX3000 contains a voltage to current converter that serves as the interface between the voltage output of the digital video processor and the current input of the east-west stage of the vertical deflection amplifier (TDA8358). The transconductance is determined by the value of an external resistor. 2004 Oct 04 14 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 2 Overview of data link modes DATA LINK 1 MODE APPLICATION VIDEO1 0 1 8 standard YUV 2fH input CVBS/Yprim C Yyuv AUDIO1 L1 L1 R1 U VIDEO2 U,V V AUDIO2 L2 L2 VIDEO3 2nd SIF 2nd SIF DATA LINK 2 PNX3000 DATA LINK 3 TEST HV_P HV_P HV_S HV_S R1 Yyuv R2 CVBSsec R2 CVBSsec I2C-BUS SPECIFICATION The slave addresses of the IC are given in Table 3. The circuit operates at clock frequencies of up to 400 kHz. Table 3 A6 1 Slave addresses (9A or 9E) A5 0 A4 0 A3 1 A2 1 A1 A1 A0 1 R/W 1/0 Bit A1 is controlled via the ADR pin, when the pin is connected to ground A1 = 0 and when connected to the positive supply line A1 = 1. When this pin is left open it is connected to ground via an internal resistor. 8.1 Input control registers Input control registers; valid subaddresses: 00 to 0F; auto-increment mode available for subaddresses SUB ADDR 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F DATA BYTE D7 AFN IFON IFGT VA1 FXT SF7 BPUV DRND SEC3 VIM 0 0 MONO DSG 0 1(1) D6 AFW DSIF VAI VA0 IFA SF6 BPY 0 SEC2 VSW MA2 RSEL SEA2 A1S2 M2G IM6 D5 IFS DFIF IFO5 TTO5 IFB SF5 BPP 0 SEC1 CMS MA1 MAT SEA1 A1S1 AMX IM5 D4 AGCM DTV IFO4 TTO4 IFC SF4 GD HDTV SEC0 CMP MA0 DVD SEA0 A1S0 M1G IM4 D3 FFI IFLH IFO3 TTO3 0 SF3 SLPM 0 PRI3 CVA3 CVB3 0 MNM1 MNM0 MICON IM3 D2 PMOD SYNT IFO2 TTO2 0 SF2 BPS 0 PRI2 CVA2 CVB2 0 PRA2 A0S2 A2S2 IM2 D1 AGC1 SSIF IFO1 TTO1 0 SF1 ST1 0 PRI1 CVA1 CVB1 CMR PRA1 A0S1 A2S1 IM1 D0 AGC0 QSS IFO0 TTO0 0 SF0 ST0 DM PRI0 CVA0 CVB0 CLPS PRA0 A0S0 A2S0 IM0 POR VALUE (HEX) 00 00 20 20 80 00 00 00 00 36 76 00 00 00 00 80 Table 4 FUNCTION Vision IF 0 Vision IF 1 IF PLL offset IF tuner take over IF PLL frequency IF synthesizer frequency Filters Data link mode Video switches 0 Video switches 1 Video switches 2 and audio mute RGB switches Audio switches ADC Audio switches 0 Audio switches 1 IRQ mask status byte 0 Note 1. The value of this bit cannot be changed. 2004 Oct 04 15 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 5 AFN 0 1 Table 6 AFW 0 1 Table 7 IFS 0 1 Table 8 AGCM 0 1 Table 9 FFI 0 1 internal external Fast filter IF PLL CONDITION normal time constant increased time constant normal reduced Internal or external AGC mode MODE normal enlarged IF sensitivity IF SENSITIVITY 0 0 1 1 0 1 0 1 DTV second IF DTV first IF 2nd SIF internal spare normal operation AFC not active AFC window AFC WINDOW AFC switch MODE Table 12 IF amplifier on/off IFON 0 1 normal operation MODE IF amplifier not active PNX3000 Table 13 Selection of signal on analog DTV output DSIF DFIF MODE LPF ACTIVE Y N N N/A Table 14 Vision IF input select DTV 0 1 VIF input DTVIF input MODE Table 15 Calibration of IF PLL demodulator IFLH 0 1 MODE calibration system active calibration system not active Table 16 IF PLL mode SYNT MODE normal mode synthesizer mode Table 10 Video modulation standard PMOD 0 1 CONDITION negative modulation (FM sound) positive modulation (AM sound) 0 1 Table 17 Second sound IF input SSIF MODE internal input external input Table 11 IF AGC speed AGC1 0 0 1 1 AGC0 0 1 0 1 0.7 x norm norm 3 x norm 6 x norm AGC SPEED 0 1 Table 18 Sound operation QSS 0 1 intercarrier sound quasi split sound MODE 2004 Oct 04 16 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 19 IF AGC operation mode IFGT 0 1 Note 1. Gated operation improves weak signal performance. Gated operation is automatically disabled if CVBS_IF is not selected as primary or secondary video signal. In this situation bit IFLH should be set to 1 to avoid recalibration of the IF VCO for white video patterns. Table 20 CVBS IF output signal amplitude correction for system I MODE VAI PMOD = 0 0 1 no correction amplitude +8 % PMOD = 1 no correction amplitude -8 % MODE non gated operation gated operation; note 1 Table 24 External reference frequency FXT 0 1 13.5 MHz 27 MHz CONDITION PNX3000 Table 25 PLL demodulator frequency setting IFA 0 0 0 0 1 1 IFB 0 0 1 1 0 1 IFC 0 1 0 1 0 0 IF FREQUENCY 58.75 MHz 45.75 MHz 38.90 MHz 38.00 MHz 33.40 MHz 33.90 MHz Table 26 IF VCO synthesizer frequency (SF7 to SF0); note 1 SF7 TO SF0 (DECIMAL NUMBER) 95 255 Note 1. fsynth = (N + 1) x 250 kHz; where 95 N 255. Table 27 Bypass UV anti-alias filters f = 24 MHz f = 64 MHz FREQUENCY Table 21 IF PLL offset adjustment IFO5 TO IFO0 (HEX) 00 20 3F tbf no correction tbf CONTROL Table 22 CVBS IF output signal amplitude BPUV OUTPUT SIGNAL AMPLITUDE VA1 0 0 1 1 VA0 PMOD = 0 0 1 0 1 no correction spare amplitude -5 % amplitude +5 % PMOD = 1 no correction spare amplitude +5 % amplitude -5 % Table 28 Bypass Yyuv anti-alias filter BPY 0 1 normal operation Yyuv anti-alias filter bypass MODE 0 1 normal operation UV anti-alias filters bypass MODE Table 23 IF AGC tuner take over TTO5 TO TTO0 (HEX) 3F 00 CONTROL tuner take over at IF input signal of 0.4 mV tuner take over at IF input signal of 80 mV Table 29 Bypass anti-alias filters of primary CVBS BPP 0 1 normal operation primary CVBS anti-alias filters bypass MODE 2004 Oct 04 17 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 30 Group delay correction GD 0 1 MODE group delay correction bypass group delay correction active Table 36 Data link modes; note 1 DM 0 1 Note MODE 2nd SIF LPF active 2nd SIF LPF bypass (for FM radio 10.7 MHz) SEC3 Table 32 Bypass anti-alias filters of secondary CVBS BPS 0 1 normal operation secondary CVBS anti-alias filters bypass MODE 0 0 0 0 1 Table 33 Sound trap frequency ST1 0 0 1 1 ST0 0 1 0 1 5.5 MHz 4.5 MHz 6.0 MHz 6.5 MHz FREQUENCY 0 1 0 SEC2 0 0 0 0 0 1 1 1 other SEC1 0 0 1 1 1 0 0 0 SEC0 0 1 0 1 1 0 0 1 Normal YUV 2fH APPLICATION PNX3000 MODE 0 1 Table 31 2nd SIF LPF mode SLPM 0 1 1. See Table 2 in Chapter "Functional description". Table 37 Selection of secondary video signal SELECTED SIGNAL CVBS_IF CVBS1 CVBS2 CVBS3 Y + C3 CVBS4 Y + C4 CVBS_DTV CVBS_IF Table 38 Selection of primary video channel PRI3 0 0 0 0 1 0 1 1 PRI2 0 0 0 0 0 1 1 1 other PRI1 0 0 1 1 1 0 0 1 PRI0 0 1 0 1 1 0 0 0 SELECTED SIGNAL CVBS_IF CVBS1 CVBS2 CVBS3 Y + C3 CVBS4 Y + C4 YC_COMB CVBS_IF Table 34 Data link transmitter test mode DRND 0 1 Note 1. The pseudo random mode can be used for in-circuit testing of the data link connections between data link transmitter in the analog front end IC and data link receiver in the digital video processor IC. Table 35 YUV 2fH clamp pulse timing HDTV 0 1 MODE normal timing (480p signal) HDTV timing (1080i signal) normal operation pseudo random test mode; note 1 MODE Table 39 Video ident mode VIM 0 1 MODE ident coupled to CVBS_IF ident coupled to selected primary CVBS signal Table 40 IF video mute VSW 0 1 2004 Oct 04 18 normal operation CVBSOUTIF muted MODE Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 41 Clamp mode secondary CVBS channel CMS 0 1 MODE top sync clamping mode black level clamping mode 0 0 Table 42 Clamp mode primary CVBS channel CMP 0 1 MODE top sync clamping mode black level clamping mode 0 0 1 0 1 Table 43 Selection of CVBS output A CVA3 0 0 0 0 1 0 1 0 CVA2 0 0 0 0 0 1 1 1 other Table 44 Mute SCART2 audio output MA2 0 1 normal operation SCART2 audio output muted MODE CVA1 0 0 1 1 1 0 0 0 CVA0 0 1 0 1 1 0 0 1 SELECTED SIGNAL CVBS_IF CVBS1 CVBS2 CVBS3 Y + C3 CVBS4 Y + C4 CVBS_DTV output muted Table 49 RGB/YUV input mode MAT 0 0 1 1 Notes DVD 0 1 0 1 RSEL 0 1 RGB1 input RGB2 input 0 0 0 0 0 0 1 1 1 other Table 48 Selection of RGB/YUV input 0 0 1 1 1 0 0 0 0 1 0 1 1 0 0 1 Table 47 Selection of CVBS output B CVB3 CVB2 CVB1 CVB0 PNX3000 SELECTED SIGNAL CVBS_IF CVBS1 CVBS2 CVBS3 Y + C3 CVBS4 Y + C4 CVBS_DTV output muted SELECTED SIGNAL MODE YUV input; note 1 YPbPr input; note 2 RGB input; note 3 spare 1. YUV input is an Y, -(B-Y) and -(R-Y) input with the specification: a) Y = 1.43 V (p-p); U = 1.33 V (p-p); V = 1.05 V (p-p). b) These signal amplitudes are based on a colour bar signal with 75 % saturation. 2. YPbPr input with the specification: a) Y = 1.0 V (p-p); Pb = 0.7 V (p-p); Pr = 0.7 V (p-p). b) These signal amplitudes are based on a colour bar signal with 100 % saturation. 3. RGB input with the specification: a) R = 0.7 x VB-W; G = 0.7 x VB-W; B = 0.7 x VB-W. b) These signal amplitudes are based on a colour bar signal with 100 % saturation. Table 45 Mute SCART1 audio output MA1 0 1 normal operation SCART1 audio output muted MODE Table 46 Mute LINE audio output MA0 0 1 normal operation LINE audio output muted MODE 2004 Oct 04 19 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 50 Clamp mode for RGB and YUV signals CMR 0 1 MODE top sync clamp mode black level clamp mode 0 Table 51 Clamp pulse selection for RGB and YUV signals CLPS 0 1 MODE clamp pulse of primary channel clamp pulse of secondary channel 0 0 1 1 1 Table 52 Selection of secondary audio channel SEA2 0 0 0 0 1 1 1 1 Note 1. Selection between AMint and AMext must be done by digital video processor. Table 53 Secondary audio channel mode MONO 0 1 1 1 1 Note 1. Mono is (L + R)/2; when AM is selected in Table 52, mono is AMint for SEA[2:0] = 000 and AMext for SEA[2:0] = 111. A more comprehensive table can be found in the application note. MNM1 - 0 0 1 1 MNM0 - 0 1 0 1 MODE stereo; see Table 52 mono (L) and AMint (R); note 1 mono (L) and AMext (R); note 1 mono (L) and MIC1 (R); note 1 mono (L) and MIC2 (R); note 1 SEA1 0 0 1 1 0 0 1 1 SEA0 0 1 0 1 0 1 0 1 SELECTED SIGNAL AMint (L) and AMext (R); note 1 L1 and R1 L2 and R2 L3 and R3 L4 and R4 L5 and R5 MIC1 (L) and MIC2 (R) AMext (L) and AMint (R); note 1 Note 0 1 1 0 0 1 1 0 1 0 1 1 PNX3000 Table 54 Selection of primary audio channel PRA2 0 PRA1 0 PRA0 0 SELECTED SIGNAL AMint (L) and AMext (R); note 1 L1 and R1 L2 and R2 L3 and R3 L4 and R4 L5 and R5 AMext (L) and AMint (R); note 1 1. Selection between AMint and AMext must be done by digital video processor. Table 55 Gain from DSND inputs to SCART outputs DSG 0 1 GAIN 0 dB; to be used with 5 V audio supply 6 dB; to be used with 8 V audio supply Table 56 Selection of SCART1 audio output AMX 0 0 0 0 0 0 0 0 1 A1S2 0 0 0 0 1 1 1 1 0 A1S1 0 0 1 1 0 0 1 1 0 A1S0 0 1 0 1 0 1 0 1 0 SELECTED SIGNAL AMint LR1 LR2 LR3 LR4 LR5 DSND1 DSND2 AMext 2004 Oct 04 20 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 57 Selection of LINE audio output AMX 0 0 0 0 0 0 0 0 1 A0S2 0 0 0 0 1 1 1 1 0 A0S1 0 0 1 1 0 0 1 1 0 A0S0 0 1 0 1 0 1 0 1 0 SELECTED SIGNAL AMint LR1 LR2 LR3 LR4 LR5 DSND1 DSND2 AMext PNX3000 Table 61 Selection of SCART2 audio output AMX 0 0 0 0 0 0 0 0 1 A2S2 0 0 0 0 1 1 1 1 0 A2S1 0 0 1 1 0 0 1 1 0 A2S0 0 1 0 1 0 1 0 1 0 SELECTED SIGNAL AMint LR1 LR2 LR3 LR4 LR5 DSND1 DSND2 AMext. Table 58 Microphone input 2 gain M2G 0 1 low high GAIN Table 62 IRQ mask bits for status byte 0 IM6 TO IM0 0 1 IRQ OUTPUT(1) IRQ output not activated IRQ output is activated when the corresponding status bit changes value Table 59 Microphone input 1 gain M1G 0 1 low high GAIN Note 1. The IRQ output is always activated if status bit POR = 1. Table 60 Microphone amplifiers on/off MICON 0 1 8.2 normal operation Output status registers MODE microphone amplifiers not active Table 63 Output status registers; subaddresses must not be sent, they are automatically incremented FUNCTION Status byte 0 Status byte 1 Reserved Status byte 3 SUB ADDR 00 01 02 03 DATA BYTE D7 POR 0 0 ID7 D6 0 0 ID6 D5 0 0 ID5 D4 ROK 0 0 ID4 D3 LOCK 0 0 ID3 D2 VID DCF 0 ID2 D1 AFA 0 0 ID1 D0 AFB AGC 0 ID0 MSUP ASUP 2004 Oct 04 21 Philips Semiconductors Preliminary specification Analog front end for digital video processors Table 64 Power-on-reset POR 0 1 normal Power-down CONDITION Table 70 AFC output AFA 0 0 1 Table 65 Main supply MSUP 0 1 main supply OK CONDITION main supply not OK Table 71 Data link current test DCF 0 Table 66 Audio supply ASUP 0 1 audio supply OK CONDITION audio supply not OK Table 72 Tuner AGC output AGC 0 Table 67 Reference frequency ROK 0 1 CONDITION reference frequency not present reference frequency present Table 73 Mask version indication ID7 0 Table 68 IF PLL lock indication LOCK 0 1 IF PLL locked INDICATION IF PLL not locked 0 0 0 0 0 Table 69 Video identification VID 0 1 INDICATION no video signal detected video signal detected 0 ID6 0 0 0 0 0 0 0 ID5 0 0 0 0 1 1 1 ID4 0 0 1 1 0 0 1 ID3 0 1 0 1 0 1 0 - 1 INDICATION tuner gain reduction active no gain reduction of tuner 1 INDICATION data link current test OK data link current test FAIL 1 AFB 0 1 0 1 PNX3000 CONDITION outside window; too low outside window; too high in window; below reference in window; above reference MASK VERSION N1A or N1B version N1C version N1D version N1E or N1F version N2B version N3B version 2004 Oct 04 22 Philips Semiconductors Preliminary specification Analog front end for digital video processors 9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VP VCC(1ASW), VCC(2ASW) Tstg Tamb Tsol Tj Vesd PARAMETER main supply voltage audio supply voltage storage temperature ambient temperature soldering temperature operating junction temperature electrostatic discharge voltage Human Body Model; C = 100 pF; R = 1.5 k pin SDA all other pins Machine Model; C = 200 pF; R = 0 k pin SDA all other pins 10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Note PARAMETER thermal resistance from junction to ambient CONDITIONS in free air; note 1 VALUE 30 - - - - - for 5 s CONDITIONS - - -25 0 - - MIN. PNX3000 MAX. 6.0 9.0 +150 70 260 150 V V UNIT C C C C 1500 2000 V V 150 200 V V UNIT K/W 1. The value given for the thermal resistance from junction to ambient should only be considered as an indication. Most of the dissipated heat is conveyed to the ambient air through the Printed-Circuit Board (PCB) on which the IC is mounted. The actual value of the thermal resistance depends on the number of metal layers, size and layout of the PCB, and also on the dissipation of other components on the PCB. 11 QUALITY SPECIFICATION In accordance with document "SNW-FQ-611". 11.1 Latch-up performance At Tamb = 70 C all pins meet the following specification: * Positive stress test: Itrigger 100 mA or Vtrigger 1.5 VP(max) * Negative stress test: Itrigger -100 mA or Vtrigger -0.5 VP(max). 2004 Oct 04 23 Philips Semiconductors Preliminary specification Analog front end for digital video processors 12 CHARACTERISTICS VCC = 5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies POWER SUPPLIES VP IP VCC(1ASW), VCC(2ASW) ICC(ASW) VCC(SUP) VCC(ASW1) Ptot VBGDEC VRREF VVD2V5 VPOR main supply voltage main supply current audio supply voltage audio supply current minimum required voltage to set status bit MSUP minimum required voltage to set status bit ASUP total power dissipation note 1 note 1 4.75 - 4.75 - - - - 2.20 2.19 2.35 1.8 5.0 285 8.0 3.5 4.0 4.0 1.45 PARAMETER CONDITIONS MIN. TYP. PNX3000 MAX. UNIT 5.25 320 8.4 5.0 - - 1.70 V mA V mA V V W REFERENCE VOLTAGES bandgap decoupling voltage on pin BGDEC voltage on pin RREF digital supply decoupling voltage at pin VD2V5 Power-On Reset (POR) level on pin VD2V5 2.30 2.30 2.50 2.0 2.40 2.41 2.65 2.2 V V V V VOLTAGE REGULATORS VAUDO, VDEFLO VAUDS, VDEFLS output voltage range voltage at feedback pin note 2 1.25 1.24 - 1.27 3.30 1.31 V V Video IF circuit VIDEO IF AMPLIFIER INPUTS Vi(dif)(rms) input sensitivity (differential; RMS value) AGC set fi = 38.9 MHZ fi = 45.75 MHz fi = 58.75 MHz Ri(dif) Ci(dif) Gv input resistance (differential) input capacitance (differential) gain control range note 3 note 3 - - - - - 64 150 75 75 75 2 3 - - 150 150 150 - - - - V V V k pF dB mV Vi(max)(dif)(rms) maximum input signal (differential; RMS value) 2004 Oct 04 24 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL fVCO fcr(PLL) td(ident) Vo(z) Vo(ts) Vo(w) Vo(dem)(p-p) Vo PARAMETER CONDITIONS MIN. -500 1 - - - 1.3 - 1.8 - - - - 3.5 1.1 1.4 3.4 2.0 0 TYP. PNX3000 MAX. UNIT PLL DEMODULATOR; NOTES 4 AND 5 free-running frequency offset of VCO catching range PLL delay time of identification PLL not locked; deviation from nominal setting without SAW filter; referred to selected IF system frequency bit LOCK = 1 0 - 20 - - 1.5 - 2.2 15 kHz MHz ms VIDEO AMPLIFIER OUTPUT: PIN CVBSOUTIF; NOTE 6 zero signal output level top sync level white level negative modulation; note 7 positive modulation; note 7 negative modulation positive modulation V V V V V % demodulated CVBS output recommended settings for bits signal (peak-to-peak value) VA1 and VA0; note 8 difference in amplitude between negative and positive modulation video output impedance internal bias current of NPN emitter follower output transistor maximum source current bandwidth of demodulated video output signal differential gain differential phase video non-linearity white spot clamp level noise inverter clamping level noise inverter insertion level intermodulation at `blue' note 12 note 12 notes 10 and 13 Vo at 0.92 MHz or 1.1 MHz Vo at 2.66 MHz or 3.3 MHz at -3 dB; before sound trap negative modulation; note 9 positive modulation; note 9 notes 9 and 10 note 11 recommended settings for bits VA1 and VA0; note 8 Zo(v) Ibias(int) - - 150 0.9 250 - mA Isource(max) Bv(-3dB) Gdif dif NLvid Vclamp Nclamp Nins dblue - 6 - - - - - - - - 9 2 3 - - 3.8 0.9 2.3 1 - 5 5 5 5 - - - mA MHz % % deg % V V V 60 60 56 60 - 56 49 - 66 66 62 66 - 60 53 5.5 - - - - - - - - dB dB dB dB dB dB mV dyellow intermodulation at `yellow' notes 10 and 13 Vo at 0.92 MHz or 1.1 MHz Vo at 2.66 MHz or 3.3 MHz S/N signal-to-noise ratio notes 10 and 14 weighted unweighted Vrc 2004 Oct 04 residual carrier signal note 10 25 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL Vrc(2H) PARAMETER residual 2nd harmonic of carrier signal note 10 CONDITIONS - MIN. TYP. 2.5 - PNX3000 MAX. UNIT mV IF AND TUNER AGC; NOTE 15 Timing of IF AGC MVI tres modulated video interference response time 30 % AM for 1 V to 100 mV; 0 Hz to 200 Hz (B/G standard) IF input signal amplitude increase of 52 dB; positive and negative modulation; IF AGC time constant set to normal IF input signal amplitude decrease of 52 dB negative modulation positive modulation - - - 50 100 - - 0.8 ms ms - - - 2 10 - % ms Tuner take over adjustment (via I2C-bus) Vstart(min)(rms) minimum starting level for tuner take over (RMS value) 0.4 mV Vstart(max)(rms) maximum starting level for tuner take over (RMS value) 100 150 - mV Tuner control output Vo(max) Vo(sat) Io(TUNERAGC) IL Vi maximum tuner AGC output voltage output saturation voltage tuner AGC output current range leakage current RF AGC input signal variation for complete tuner control maximum tuner gain; note 3 minimum tuner gain; Io = 1 mA - - 0 - 0.5 - - - - 2 5 300 1 1 4 V mV mA A dB AFC OUTPUT (VIA I2C-BUS); NOTE 16 fAFC fw flw DTV IF circuit DTV IF AMPLIFIER INPUT Vi(dif)(rms) Ri(dif) input sensitivity (differential; RMS value) input resistance (differential) fi between 30 MHz and 60 MHz - note 3 - 75 2 150 - V k AFC resolution window sensitivity window sensitivity in large window mode - - - 2 125 275 - - - bits kHz kHz 2004 Oct 04 26 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL Ci(dif) Gv PARAMETER input capacitance (differential) gain control range note 3 CONDITIONS - 64 150 MIN. 3 - - TYP. - - - PNX3000 MAX. UNIT pF dB mV Vi(max)(dif)(rms) maximum input signal (differential; RMS value) DTV IF MIXER fosc N(osc) PBll PBul PBR Bsb sb Vi Zi Vo(dif)(p-p) oscillator frequency oscillator phase noise lower limit pass-band upper limit pass-band pass-band ripple stop band stop band attenuation step size 250 kHz carrier to noise ratio in dBc/Hz 24 - - 10.0 - - 40 - -92 - - - 44 - - - 64 - 1.0 - 0.5 - - 3 - MHz dB MHz MHz dB MHz dB EXTERNAL AGC CONTROL voltage range for full control of the amplifier input impedance 1 1 V M DTV OUTPUT (DOWN-MIXED OUTPUT SIGNAL) differential output signal (peak-to-peak value) internal AGC mode; no modulation DTV 1st IF mode; f = 40 MHz - DTV 2nd IF mode; f = 4 MHz - Vo(dif)(p-p)(max) maximum allowed differential output signal (peak-to-peak value) Zo(dif) VO Ibias(int) Isource(max) output impedance (differential) DC output level internal bias current of emitter followers maximum allowed source current DTV 1st IF mode DTV 2nd IF mode external AGC mode; note 17 DTV 1st IF mode; f = 40 MHz - DTV 2nd IF mode; f = 4 MHz - - - - - - 0.95 1.68 150 1.15 3.0 2 - - - - - - - 2 V V V V mA mA 0.68 1.20 - - V V Sound IF circuit SOUND IF AMPLIFIER Vi(rms) Vi(max)(rms) Ri(dif) input sensitivity (RMS value) maximum input signal (RMS value) input resistance (differential) note 3 -3 dB - tbf - 45 100 2 tbf - - dBV dBV k 2004 Oct 04 27 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL Ci(dif) Gv ct(SIF-VIF) PARAMETER input capacitance (differential) gain control range crosstalk attenuation between SIF and VIF input note 3 CONDITIONS - - 50 MIN. 3 55 - TYP. - - - PNX3000 MAX. UNIT pF dB dB SOUND IF INTERCARRIER OUTPUT ON DTV OUTPUT, FM MODULATION; NOTE 18 Vo(dif)(rms) B-3dB Vr(SC)(rms) Zo(dif) VO Ibias(int) Isource(max) S/NW differential output signal amplitude (RMS value) bandwidth (-3 dB) residual IF sound carrier (RMS value) output impedance (differential) DC output voltage internal bias current of emitter followers maximum allowed source current weighted S/N ratio (SC1/SC2) ratio of PC/SC1 at vision IF input of 40 dB or higher; note 19 black picture white picture 6 kHz sinewave (black-to-white modulation) 250 kHz sine wave (black-to-white modulation) sound carrier subharmonics (f = 2.75 MHz 3 kHz) sound carrier subharmonics (f = 2.87 MHz 3 kHz) AM SOUND OUTPUT; NOTE 20 Vo(rms) THD B-3dB S/NW PSRR AF output signal amplitude 54 % modulation (RMS value) total harmonic distortion -3 dB AF bandwidth weighted signal-to-noise ratio power supply ripple rejection ratio 54 % modulation 5 V main supply 54 % modulation 80 % modulation 400 - - 100 47 - 500 0.5 tbf 125 53 17 600 1.0 5.0 - - - mV % % kHz dB dB 53/48 52/47 44/42 44/25 45/44 46/45 58/55 55/53 48/46 48/30 51/50 52/51 - - - - - - dB dB dB dB dB dB SC1; sound carrier 2 off 75 7.5 - - - - - 100 8.5 2 150 1.3 2 2 125 - - - - - - mV MHz mV V mA mA 2004 Oct 04 28 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER CONDITIONS MIN. TYP. PNX3000 MAX. UNIT 2nd sound IF AGC circuit 2ND SOUND IF EXTERNAL INPUT Vi(rms) fi Ri Ci G Ich(AGC) Idch(AGC) input voltage range (RMS value) input frequency range input resistance input capacitance note 21 note 3 note 3 18 4 - - - FM mode AM mode discharge current AGC pin FM mode AM mode overload DIGITAL OUTPUT nd(p-p) decimal digital output level (peak-to-peak value) FM mode AM mode; no modulation - - 716 358 - - - - - - - - - 25 3 320 10.7 - - - 12.5 2.5 50 2.5 - mV MHz k pF 2ND SOUND IF AGC gain control range charge current AGC pin 25 - - - - 1 dB A A A A mA Sound trap and group delay correction filter SOUND TRAP Bv(-3dB) -3 dB video bandwidth (sound trap + group delay) fSC1 = 4.5 MHz fSC1 = 5.5 MHz fSC1 = 6.0 MHz fSC1 = 6.5 MHz Vchrom(p) SC1 SC2 peaking at chroma subcarrier frequency attenuation at first sound carrier fSC1 attenuation at second sound carrier fSC2 all trap frequencies f = 4.726 MHz; fSC1 = 4.5 MHz f = 5.742 MHz; fSC1 = 5.5 MHz f = 6.55 MHz; fSC1 = 6.0 MHz f = 6.742 MHz; fSC1 = 6.5 MHz GROUP DELAY CORRECTION; FIGURES 6 AND 7; NOTE 22 td(g) group delay f = 4.43 MHz; sound trap frequency 5.5 MHz; sound trap only f = 4.43 MHz; sound trap frequency 5.5 MHz; sound trap plus group delay correction filter - 180 - ns 3.90 4.80 5.25 5.70 - 28 21 21 12 18 4.00 4.90 5.35 5.80 1.0 33 27 27 18 24 - - - - 2.0 - - - - - MHz MHz MHz MHz dB dB dB dB dB dB - 170 - ns 2004 Oct 04 29 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL Video switches CVBS AND YC SWITCHES Vi(CVBS/Y)(p-p) Vi(CVBS/Y)(clip) Ii(CVBS/Y) sup(CVBSn) CVBS or Y input voltage (peak-to-peak value) CVBS or Y clipping level CVBS or Y input current suppression of non-selected CVBS input signal chrominance input voltage (peak-to-peak value) chrominance input impedance black-to-peak video outside clamp pulse during clamp pulse note 10 - - - -10 50 1.0 1.33 0 - - PARAMETER CONDITIONS MIN. TYP. PNX3000 MAX. UNIT 1.76 - - +10 - V V A A dB Vi(C)(p-p) Zi(C) 100 % colour bar; note 3 - - 885 50 1264 - mV k VIDEO IDENT FUNCTION Vsync(min) td(ident) minimum sync pulse amplitude delay time of identification 70 I2C-bus status bit VID = 1; after - the Video IF AGC has stabilized on a new transmitter - at input signal of 1.0 V (p-p) top sync output muted DIGITAL OUTPUTS - - - 100 - 140 10 mV ms ANALOG CVBS OUTPUTS: PINS CVBSOUTA AND CVBSOUTB Zo Vo(p-p) VO output impedance output signal amplitude (peak-to-peak value) DC output level - 2.0 0.4 0.5 250 - - - V V V CVBS/Y signal nd(black) nd(white) decimal digital output level for black decimal digital output level for white black clamp mode nominal input signal - - 240 652 - - C signal nd(black) nd(p-p) decimal digital output level for black decimal digital output amplitude (peak-to-peak value) nominal input level; 100 % colour bar 480 - 512 520 544 - 2004 Oct 04 30 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER CONDITIONS MIN. TYP. PNX3000 MAX. UNIT RGB, YPbPr and YUV inputs ANALOG INPUTS General Ii input current outside clamp pulse during clamp pulse - -10 - 0 - 0.7 - +10 A A V RGB mode Vi(b-w) input signal amplitude (black-to-white value) 1.0 YPbPr mode Vi(Y)(p-p) Vi(Pb)(p-p) Vi(Pr)(p-p) Y input signal amplitude (peak-to-peak value) Pb input signal amplitude (peak-to-peak value) Pr input signal amplitude (peak-to-peak value) top sync-to-white 100 % colour bar 100 % colour bar - - - 1.0 0.7 0.7 1.43 1.0 1.0 V V V YUV mode Vi(Y) Vi(U)(p-p) Vi(V)(p-p) Y input signal amplitude U input signal amplitude (peak-to-peak value) V input signal amplitude (peak-to-peak value) top sync-to-white 100 % colour bar 100 % colour bar - - - 1.43 1.77 1.40 2.04 2.53 2.00 V V V DIGITAL OUTPUTS General td delay difference for the three channels note 10 - 0 20 ns Y signal nd(black) nd(white) decimal digital output level for black decimal digital output level for white black clamp mode nominal input level - - 240 788 - - U and V signals; note 23 nd(black) nd(p-p) decimal digital output level for black decimal digital output amplitude (peak-to-peak value) black clamp mode nominal input level; 100 % colour bar - - 512 716 - - Video anti-alias filters CVBS, YYC, C AND 2ND SIF FILTERS fpb(-1dB) -1.0 dB pass-band frequency - 8.0 - MHz 2004 Oct 04 31 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL fpb(-3dB) fsb(-35dB) td(g) EG E S/N YYUV FILTERS fpb(-1dB) fpb(-3dB) fsb(-35dB) td(g) -1.0 dB pass-band frequency -3.0 dB pass-band frequency -35 dB stop band frequency group delay 1fH mode 2fH mode 1fH mode 2fH mode 1fH mode 2fH mode at 1 MHz; 1fH mode at 1 MHz; 2fH mode at 5 MHz; 1fH mode at 10 MHz; 2fH mode S/N signal-to-noise ratio - - - - - - - - - - 8.0 16 9.0 18 20 40 36 18 42 21 - - - - - - - - - - - - PARAMETER -3.0 dB pass-band frequency -35 dB stop band frequency group delay differential gain error differential phase error signal-to-noise ratio at 1.0 MHz at 5.0 MHz note 9 notes 9 and 10 B = 5 MHz; note 24 CONDITIONS - - - - - - 60 MIN. TYP. 9.0 20 36 42 2 - - - - - - 5 5 - PNX3000 MAX. UNIT MHz MHz ns ns % deg dB MHz MHz MHz MHz MHz MHz ns ns ns ns dB 1fH mode: B = 5 MHz 60 2fH mode: B = 10 MHz; note 24 1fH mode 2fH mode 1fH mode 2fH mode 1fH mode 2fH mode at 1 MHz; 1fH mode at 1 MHz; 2fH mode at 2.5 MHz; 1fH mode at 5 MHz; 2fH mode - - - - - - - - - - U AND V FILTERS fpb(-1dB) fpb(-3dB) fsb(-35dB) td(g) -1.0 dB pass-band frequency -3.0 dB pass-band frequency -35 dB stop band frequency group delay 4.0 8.0 4.5 9.0 10 20 72 36 84 42 - - - - - - - - - - - - MHz MHz MHz MHz MHz MHz ns ns ns ns dB S/N signal-to-noise ratio 1fH mode: B = 5 MHz 60 2fH mode: B = 10 MHz; note 24 - - FILTER FOR DTV 2ND IF SIGNAL fpb(-1dB) fpb(-3dB) -1.0 dB pass-band frequency -3.0 dB pass-band frequency 10 12 - - MHz MHz 2004 Oct 04 32 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL fsb(-35dB) td(g) S/N PARAMETER -35 dB stop band frequency group delay signal-to-noise ratio B = 10 MHz; note 25 CONDITIONS - - - 60 Video analog-to-digital converters GENERAL; NOTE 26 Bv(-3dB) fsample RES -3 dB signal bandwidth sample frequency resolution 1fH mode 1fH mode - - - fclk = 54 MHz; fsignal = 10 MHz fclk = 54 MHz; fsignal = 10 MHz fclk = 27 MHz; fsignal = 5 MHz fclk = 54 MHz; fsignal = 10 MHz S/N ENOB signal-to-noise ratio effective number of bits fclk = 27 MHz; B = 5 MHz fclk = 54 MHz; B = 10 MHz fclk = 54 MHz; fsignal = 10 MHz Audio selectors LR INPUTS Vi(max)(rms) Ri G (LRn) maximum input voltage (RMS value) input resistance gain from LR inputs to analog outputs crosstalk attenuation from non-selected inputs outputs unloaded f = 10 kHz 5 V audio supply 8 V audio supply 1.0 2.0 24 -0.4 70 - - 32 0 80 - - - - - - - - - - 9 27 10 - - - - - - - - - - MIN. TYP. 44 22 32 - - - - - PNX3000 MAX. UNIT MHz ns ns dB MHz MHz bit STATIC MEASUREMENTS DNL INL differential non-linearity integral non-linearity 0.7 1 -63 -63 58 58 9.0 LSB LSB DYNAMIC MEASUREMENTS THD total harmonic distortion dB dB dB dB bits V V k dB dB +0.3 - DSND INPUTS FOR AUDIO SIGNALS COMING FROM DIGITAL VIDEO PROCESSOR Vi(max)(rms) Ri G maximum input signal amplitude (RMS value) input resistance gain from DSND inputs to analog outputs 5 V audio supply; DSG = 0; outputs unloaded 8 V audio supply; DSG = 1; outputs unloaded (DSNDn) crosstalk attenuation from non-selected inputs 1.0 24 -0.4 5.6 70 - 32 0 6.0 80 - - +0.3 6.3 - V k dB dB dB MICROPHONE AMPLIFIERS; NOTE 27 Ri input resistance - 20 - k 2004 Oct 04 33 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL Glow Ghigh f THD + N S/N PARAMETER low gain high gain frequency range total harmonic distortion plus noise signal-to-noise ratio 1 kHz input signal at 0.9 V (RMS) output level referred to 16 mV (RMS) input level; low gain referred to 16 mV (RMS) input level; high gain ANALOG OUTPUTS Vo(max)(rms) Zo THD + N maximum output signal amplitude (RMS value) output impedance total harmonic distortion plus noise 1 kHz input signal +6 dBV output level -54 dBV output level; A-weighted S/N f PSRR signal-to-noise ratio frequency range power supply ripple rejection ratio 1 kHz ripple frequency ripple on 5 V main supply ripple on 8 V audio supply Audio analog-to-digital converters DIGITAL AUDIO OUTPUTS; NOTE 28 Vi(max)(rms) THD + N maximum input voltage (RMS value) total harmonic distortion plus noise 5 V audio supply 8 V audio supply 1 kHz input signal +0 dBV output level -54 dBV output level; A-weighted S/N cs Vo PSRR signal-to-noise ratio channel separation digital output level power supply ripple rejection ratio referred to 0 dBV input level; A-weighted 0 kHz to 20 kHz at 2 V (RMS) input level 8 V audio supply voltage; 1 kHz ripple frequency ripple on 5 V main supply ripple on 8 V audio supply - - 54 55 18 - - - - - - - - -78 -30 86 80 -4.3 - - - - - 1.0 2.0 - - - - - - 43 45 - - referred to 0 dBV output level; A-weighted -80 -36 90 20 -88 -40 96 - - - - 5 V audio supply 8 V audio supply 1.0 2.0 - - - 500 - - CONDITIONS bits M1G = M2G = 0 bits M1G = M2G = 1 - - 50 -74 70 74 MIN. TYP. 17 35 - -80 76 80 - - PNX3000 MAX. UNIT dB dB Hz dB dB dB 20000 - - - V V dB dB dB Hz dB dB 650 20000 V V dB dB dB dB dBFS dB dB dB 5 V audio supply voltage; 1 kHz - ripple frequency 2004 Oct 04 34 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL Timing circuit HV INPUT SIGNALS: PINS HV_PRIM AND HV_SEC; NOTES 29 AND 30 PARAMETER CONDITIONS MIN. TYP. PNX3000 MAX. UNIT Timing specification for HV pulses coming from digital video processor; see Fig.8 t(HV-sync) time between start HV pulse and start of horizontal sync pulse on CVBS/Y signal width of HV pulses 1fH TV mode 2fH mode; HDTV = 0 2fH mode; HDTV = 1 1fH TV mode normal lines clamp disable lines vsync lines 2fH mode HDTV = 0 normal lines clamp disable lines vsync lines 2fH mode; HDTV = 1 normal lines clamp disable lines vsync lines - - - - - - - - - - - - - - - 25 - 1 20 44 144 - - - - - - - - - - - - - - - 45 - 3.5 ck ck ck - - - 36 64 144 - - - ck ck ck - - - 72 128 288 - - - ck ck ck - - - 0.6 0.3 0.3 - - - s s s tW(HV) Detection of clamp disable lines tdet(clamp)(dis) clamp disable detection 1fH TV mode 2fH mode; HDTV = 0 2fH mode; HDTV = 1 80 40 24 ck ck ck Detection of vsync lines tdet(vsync) vsync detection 1fH TV mode 2fH mode; HDTV = 0 2fH mode; HDTV = 1 255 136 136 ck ck ck Internal clamp pulses td(HV-clamp) delay between start of HV pulse and start of clamp pulse width of clamp pulse 1fH TV mode 2fH mode; HDTV = 0 2fH mode; HDTV = 1 1fH TV mode 2fH mode; HDTV = 0 2fH mode; HDTV = 1 CRYSTAL REFERENCE FREQUENCY INPUT: PIN XREF Ri Ci Vi(p-p) input resistance input capacitance input signal amplitude (peak-to-peak value) 35 3 - k pF V 80 40 24 44 22 17 ck ck ck ck ck ck tW(clamp) 2004 Oct 04 35 Philips Semiconductors Preliminary specification Analog front end for digital video processors SYMBOL PARAMETER CONDITIONS MIN. TYP. PNX3000 MAX. UNIT Data link transmitters GENERAL fword(CLK) WL fD fbit(CLK) word clock frequency word length data rate bit clock frequency individual data and strobe signals - - - - 13.5 44 594 297 - - - - MHz bits Mbit/s MHz OUTPUT DRIVERS FOR DATA AND STROBE SIGNALS Vo Vo(dif)(p-p) Ro RL voltage swing (peak-to-peak value) differential output voltage (peak-to-peak value) output resistance load resistance connected between positive terminal and negative terminal individual pins; output loaded with 100 output loaded with 100 - - - - 0.3 0.6 - 100 - - 50 - V V East-west drive circuit: pins EWVIN, EWIOUT and REW Ri Vi Rew Vo Io input resistance input voltage range external conversion resistor output voltage range output current range note 31 note 31 - 0 - 1.0 0 40 - 750 - - - 3.5 - Vcc 1.2 k V V mA I2C-bus control inputs and outputs SDA/SCL INPUTS AND OUTPUT; NOTE 32 Vi VIL VIH IIL IIH VOL Ci VOL VOH Notes 1. The supply voltage for the analog audio part may have a value between 5 V and 8 V. For a supply voltage of 5 V the maximum amplitude of in- and output signals is 1 V (RMS). For a supply voltage of 8 V the maximum amplitude of in- and output signals is 2 V (RMS). 2. The value of the regulated voltage is determined by the external resistive voltage divider. The voltage range mentioned relates to the voltage at the emitter of the external transistor. The stability of the voltage regulator loop input voltage level LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current LOW-level output voltage input capacitance Vi = 0 V Vi = 5.5 V SDA pin; IL = 3 mA 0 - - - - - IRQ pin; IL = 1.5 mA open drain - - - - 0 0 - 5 - - 5.5 - - - 0.4 10 V V A A V pF 0.2 x VCC V 0.5 x VCC - IRQ OUTPUT; NOTE 33 LOW-level output voltage HIGH-level output voltage 0.4 5.5 V V 2004 Oct 04 36 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 depends on the value of the decoupling capacitor Cdec on the emitter of the external transistor. Recommended value Io is C dec = 1.5 x ----- F, with Io in mA. Vo 3. This parameter is not tested during production and is just given as application information for the designer of the television receiver. 4. Loop bandwidth BL = 60 kHz (natural fN = 15 kHz; damping factor d = 2; calculated with top sync level as IF PLL input signal level). 5. The IF PLL demodulator uses an internal VCO (no external LC-circuit required) which is calibrated by means of a digital control circuit which uses the clock frequency of the microcontroller/teletext decoder as a reference. The required IF frequency for the various standards is set via the I2C-bus. When the system is locked the resulting IF frequency is very accurate with a deviation from the nominal value of less than 25 kHz. 6. Measured at pin CVBSOUTIF with 10 mV (RMS) top sync input signal at VIF input. 7. So called projected zero point, i.e. with switched demodulator. 8. The signal amplitude at the CVBSOUTIF output depends on the setting of bits VA1 and VA0. The recommended settings for negative modulation (bit PMOD = 0) is VA1 = VA0 = 1. For positive modulation (bit PMOD = 1) the settings VA1 = 1 and VA0 = 0 is recommended. The Vo(dem)(p-p) and Vo values specified are valid if the recommended settings are used. 9. Measured in accordance with the test line given in Fig.3. For the differential phase test the peak white setting is reduced to 87 %: a) The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. b) The phase difference is defined as the difference in degrees between the largest and smallest phase angle. 10. This parameter is not tested during production but is guaranteed by the design and qualified by means of matrix batches which are made in the pilot production period. 11. This figure is valid for the complete video signal amplitude (peak white-to-black), see Fig.4. 12. The noise inverter is only active in the `strong signal mode' (no noise detected in the incoming signal). 13. The test set-up and input conditions are given in Fig.5. Measurement is done with an input signal of 10 mV (RMS). 14. Measured at an input signal of 10 mV (RMS). The S/N is the ratio of black-to-white amplitude to the black level noise voltage (RMS value); B = 5 MHz. Weighted in accordance with CCIR 567. 15. The time-constant of the IF AGC is internal and the speed of the AGC can be set via bus bits AGC1 and AGC0. The AGC response time is also dependent on the acquisition time of the PLL demodulator. The values given are valid for the `norm' setting (AGC1 = 0 and AGC0 = 1) and when the PLL is in lock. 16. The AFC control voltage is generated by the digital tuning system of the PLL demodulator. This system uses the external crystal frequency as a reference and is therefore very accurate. For this reason no maximum and minimum values are given for the window sensitivity figures. The tuning information is supplied to the tuning system via the I2C-bus. Two bits are reserved for this function. The AFC value is valid only when bit LOCK = 1. 17. Exceeding this amplitude leads to intermodulation distortion. 18. The intercarrier sound (2nd SIF) signal is not normally an analog output signal of the IC. It can be made available on the DTV output pins by setting bus bits DSIF = 1 and DFIF = 0. 19. The weighted S/N ratio is measured under the following conditions: a) The vision IF modulator incidental phase modulation for black-to-white jumps must be less than 0.5 degrees b) QSS AF performance of the vision IF modulator, measured with the television demodulator AMF2 (audio output and weighted S/N ratio) better than 60 dB (deviation 27 kHz) for 6 kHz sine wave black-to-white modulation c) Picture-to-sound carrier ratio of the vision IF modulator: PC/SC1 = 13 dB (transmitter) 2004 Oct 04 37 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 d) The measurements must be carried out with the Siemens SAW filters G3962 for vision IF and G9350 for sound IF. Input level for sound IF 10 mV (RMS) with 27 kHz deviation e) The PC/SC ratio at the vision IF input is calculated as the addition of the TV transmitter ratio and the SAW filter PC/SC ratio. This PC/SC ratio is necessary to achieve the S/NW values as indicated. 20. The demodulated AM sound signal can be made available in the analog domain on LINE or SCART audio outputs by selecting AM internal (bus bit AMX = 0). 21. The frequency range of the 2nd SIF channel is limited by the 2nd SIF anti-alias filter. If a 10.7 MHz FM radio IF signal is supplied to the external 2nd SIF input; an external 10.7 MHz bandpass filter must be used; and the internal anti-alias filter must be bypassed by setting bus bit SLPM = 1. 22. The cascade of sound trap and group delay correction filter compensates for the group delay pre-distortion of the BG standard, curve A (see "Rec. ITU-R BT.470-4"). The indicated values are the difference between the group delay at 4.43 MHz and the group delay at 10 kHz. 23. The digitized U and V signals have the following polarity: U = +(B-Y) and V = +(R-Y). 24. The S/N ratio is defined as the ratio of the full scale black-to-white amplitude to the black level noise voltage (RMS value). 25. The S/N ratio is defined as the ratio of the full scale peak-to-peak signal amplitude to the zero signal noise voltage (RMS value). 26. The video ADC is specified as a stand-alone circuit. Distortion and noise of the video switch and anti-alias filters is not included. 27. The gain of the microphone amplifiers can be switched between low (17 dB) and high (35 dB). The low gain can be used for microphones with a sensitivity between 5 mV (RMS) and 40 mV (RMS) at 94 dB SPL. The high gain can be used for microphones with a sensitivity of less than 5 mV (RMS) at 94 dB SPL. 28. If the audio supply voltage is 8 V; the 5 V full scale reference voltage for the audio A to D converters at pin 91 (VAADCP) is generated by the IC itself, using the internal bandgap reference. This gives the best power supply rejection ratio for the digital audio outputs. If the audio supply voltage is 5 V; pin 91 must be connected to the external 5 V supply. This results in a reduced power supply rejection ratio for the digital audio outputs. 29. Signals HV_PRIM and HV_SEC must be generated by the digital video processor using a 13.5 MHz clock. Where pulse widths are specified in clock pulses, a 13.5 MHz clock is assumed (1 clock pulse is 74.1 ns). To enable detection of the vertical blanking interval, a larger pulse width is used for a number of lines during the vertical blanking period; see Figs 9 and 10. 30. Most timing parameters in this section are expressed in number of clock cycles, abbreviated as ck. 31. The east-west drive circuit is a voltage to current converter circuit, that requires an external conversion resistor. The open drain output transistor can only sink current. The relation between input voltage and output current is as follows: Vi I o = ------------------- where Rew is the external conversion resistor. The voltage across the external conversion resistor is 4 x R ew equal to Vi/4. The voltage at output pin EWIOUT must not be lower than Vi/4 + 0.25 V. The output current must not be larger than 1.2 mA. 32. The switching levels of pins SDA and SCL are compatible with an external signal amplitude of 3.3 V and 5 V. 33. The IRQ output is an open-drain output; active LOW. The pin IRQ must be loaded with a pull-up resistor. 2004 Oct 04 38 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 MBC212 16 % 100% 92% 30% for negative modulation 100% = 10% rest carrier Fig.3 Video output signal. handbook, full pagewidth MBC211 100 (%) 86 72 58 44 30 10 12 22 26 32 36 40 44 48 52 56 60 64 time (s) Fig.4 Test signal waveform. 2004 Oct 04 39 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 handbook, full pagewidth -3.2 dB -10 dB -13.2 dB -30 dB -13.2 dB -30 dB SC CC BLUE PC SC CC YELLOW PC MBC213 PC SC ATTENUATOR TEST CIRCUIT SPECTRUM ANALYZER CC gain setting adjusted for blue MCE436 Input signal conditions: SC = sound carrier; CC = colour carrier; PC = picture carrier. All amplitudes with respect to top sync level. V O at 3.58 MHz or 4.4 MHz Value at 0.9 MHz or 1.1 MHz = 20 log ------------------------------------------------------------------------- + 3.6 dB V O at 0.92 MHz or 1.1 MHz V O at 3.58 MHz or 4.4 MHz Value at 2.66 MHz or 3.3 MHz = 20 log ------------------------------------------------------------------------V O at 2.66 MHz or 3.3 MHz Fig.5 Test set-up intermodulation. 2004 Oct 04 40 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 handbook, full pagewidth 225 MCE431 td(g) (ns) 175 125 75 25 -25 0 1 2 3 4 f (MHz) 5 Fig.6 Group delay characteristic without group delay correction (sound trap: 5.5 MHz). handbook, full pagewidth 400 MCE432 td(g) (ns) 300 200 100 0 -100 0 1 2 3 4 f (MHz) 5 Fig.7 Group delay characteristic with group delay correction (sound trap: 5.5 MHz). 2004 Oct 04 41 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 handbook, halfpage CVBS_in handbook, halfpage normal lines 0.6 s HV pulse 5.33 s (72 ck) HGATE 5.92 s (80 ck) CLP 3.26 s (44 ck) clamp pulse position MCE434 MCE433 clamp disable lines clamp disable detection Vsync lines vert. sync detection Fig.8 Timing of some horizontal timing signals compared to incoming CVBS signal (1fH mode). Fig.9 Horizontal timing of HV pulses (1fH mode). handbook, full pagewidth line counter reset in digital decoder video second field HV pulse det no norm det first field detected V pulse video first field HV pulse det no norm det second field detected V pulse MCE435 Fig.10 Recommended vertical timing of incoming HV pulses (1fH mode). 2004 Oct 04 42 Philips Semiconductors Preliminary specification Analog front end for digital video processors 13 TEST AND APPLICATION INFORMATION 13.1 Power supply decoupling PNX3000 For optimal THD and SNR performance of the analog and digital audio channels, it is important to have stable 5 V and 8 V supply voltages for the audio part of the PNX3000. The following pins need a stable supply voltage without disturbances in the baseband audio frequency range: * Pins VCC(1ASW) and VCC(2ASW) (pins 98 and 88); the supply voltage for the analog audio switches. The supply current to both of these pins is less than 5 mA. Note that this supply voltage may be 5 V or 8 V. * Pin VAADCP (pin 91); the 5 V full scale reference for the audio ADCs. The current consumption of this pin is about 0.25 mA. This pin must only be connected to the 5 V supply if an audio supply voltage (pins VCC(1ASW) and VCC(2ASW)) of 5 V is used. If an audio supply of 8 V is used, this pin must not be connected to the 5 V supply voltage. In this case the reference voltage is generated by the IC itself, and only a decoupling capacitor should be connected to this pin. * Pin VCC(AADC) (pin 77) is the 5 V supply voltage for the audio ADCs. The supply current for this pin is about 23 mA. 2004 Oct 04 43 Philips Semiconductors Preliminary specification Analog front end for digital video processors 13.2 Application diagram VCC_audio PNX3000 handbook, full pagewidth DTV AGC control TUNERAGC ATVIFIN SAW 5.6 k 2.2 F 2.2 F 10 100 nF (2) 10 F MIC1 470 nF VCC5 220 (3) MIC2 10 F 470 nF 2.2 F 10 (2) (2) L1 R1 L2 R2 L3 VCC(1AASW) GND(1ASW) DTVIFAGC SIFAGC SIFINN SIFINP FUSE VCC(2ASW) VAADCREF VAADCN VAADCP GND(2ASW) SIFIN 100 10 (2) F nF 100 nF 100 nF 470 470 470 nF nF nF 470 470 nF nF MIC1N MIC2N MIC1P MIC2P R1 R2 83 20 L1 L2 DTVIFIN SAW DTVIFINP DTVIFINN TUNERAGC 102 101 100 103 104 105 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 SAW 1 F 82 k V 100 nF 390 CC5 100 nF (2) 106 VIFINP 107 VIFINN 108 DTVIFPLL 109 VCC(IF) 110 FUSE 100 pF 2nd SIFext 10 nF 2.2 F to DTV channel decoder 2.2 k VCC5 100 nF (2) 68 180 CVBS0 100 nF (1) 180 CVBS_IF SCART1 CVBS1 100 nF (1) VIFPLL 111 GND(1IF) 112 2NDSIFEXT 113 2NDSIFAGC 114 GND(2IF) 115 DTVOUTP 116 DTVOUTN 117 VCC(SUP) 118 FUSE 119 CVBSOUTIF 120 GND(SUP) 121 VCC(1VSW) 122 CVBS0 123 TESTPIN1 124 VCC(2VSW) 125 CVBS1 126 R5 127 L5 128 1 2 3 4 5 6 7 8 9 10 11 PNX3000 12 13 14 15 16 17 18 19 CVBS_DTV GND(FILT) C4 BGDEC CVBS/Y4 FUSE YCOMB CCOMB GND(VSW) VCC(FILT) TESTPIN3 VAUDO VAUDS CVBS/Y3 AMEXT CVBS2 C3 CVBSOUTA VDEFLO 100 nF (1) (1) (1) (1) (1) (1) (1) (1) 100 nF CVBS2 1.6 k 100 nF Y3 1.2 k C3 100 nF 100 nF Y4 C4 100 nF 100 nF (2) 100 nF VCC5 47 k 100 nF 470 nF VDEFLS RREF L3 82 21 1.8 k 1.2 k AMext A Y C 2.2 F 100 nF (2) B 3D-CMB 2.2 k VCC5 = 5 V analog supply. VCC_audio = 5 V or 8 V for audio switch matrix. (1) foil or ceramic capacitor. (2) ceramic multi-layer capacitor for supply decoupling. (3) This resistor is only used when VCC_audio = 5 V, remove if VCC_audio = 8 V. 330 68 CVBS SCART2 MCE437 Fig.11 Application diagram (continued in Fig.12). 2004 Oct 04 44 Philips Semiconductors Preliminary specification Analog front end for digital video processors PNX3000 handbook, full pagewidth VCC5 47 R3 L4 R4 (1) SCART1 L R L LINE R SCART2 R L DSND1 DSND2 22 F 470 470 470 470 nF nF nF nF GND(AADC) SCART1R DSNDR1 DSNDR2 DSNDL1 DSNDL2 SCART2R SCART1L SCART2L VCC(AADC) 470 470 470 100 nF nF nF nF 3.3 nF 3.3 nF 3.3 nF 3.3 nF 81 80 79 FUSE R3 R4 L4 78 77 76 75 74 73 72 71 70 69 68 LINER 67 LINEL FUSE 66 65 VCC(I2D) 64 63 62 61 60 59 DATA1P DATA1N STROBE1P STROBE1N GND(I2D) VCCD5 100 nF (2) ADOC or AVIP data link 1 PNX3000 DATA2P 58 DATA2N 57 STROBE2P 56 STROBE2N 55 FUSE 54 DATA3P 53 DATA3N 52 STROBE3P 51 STROBE3N 50 VCC(DIG) 49 48 47 GND(DIG) GNDD data link 2 data link 3 VCCD5 100 nF (2) 4.7 k 3.3 V 22 CVBSOUTB 23 FUSE 24 TESTPIN2 25 R1/PR1/V1 26 G1/Y1/Y1 27 B1/PB1/U1 28 VCC(RGB) 29 GND(RGB) 30 R2/PR2/V2 31 G2/Y2/Y2 32 B2/PB2/U2 33 FUSE 34 GND(VADC) 35 VCC(VADC) 36 EWVIN 37 EWIOUT 46 HV_SEC 45 SCL 44 SDA 43 IRQ 42 FUSE 41 XREF 40 ADR 39 38 REW 100 nF (2) VD2V5 GNDD HV_PRIM 4.7 k 10 k HV_PRIM HV_SEC SCL SDA IRQ fref (13.5 or 27 MHz) (1) (1) (1) 100 nF 100 nF R1 G1 100 (2) 100 nF 100 nF nF B1 VCC5 (1) (1) (1) 100 nF R2 G2 100 nF B2 (2) 750 EWVIN Vdeflection 100 nF VCC5 A B 2.2 k 4.7 F EWIOUT 4.7 F Vaudio MCE438 330 68 CVBS SCART3 VCC5 = 5 V analog supply. VCCD5 = 5 V digital supply. GNDD = digital ground. (1) foil or ceramic capacitor. (2) ceramic multi-layer capacitor for supply decoupling. Fig.12 Application diagram (continued from Fig.11). 2004 Oct 04 45 Philips Semiconductors Preliminary specification Analog front end for digital video processors 14 PACKAGE OUTLINE LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm PNX3000 SOT425-1 c y X A 102 103 65 64 ZE e E HE A A2 A 1 (A 3) Lp L detail X wM pin 1 index 128 1 wM D HD ZD B vM B 39 38 bp vM A bp e 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.15 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.20 0.09 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D(1) Z E(1) 0.81 0.59 0.81 0.59 7 o 0 o 22.15 16.15 21.85 15.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT425-1 REFERENCES IEC 136E28 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-20 2004 Oct 04 46 Philips Semiconductors Preliminary specification Analog front end for digital video processors 15 SOLDERING 15.1 Introduction to soldering surface mount packages PNX3000 with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 Manual soldering This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 15.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 seconds and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 C to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 15.3 Wave soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 seconds to 5 seconds between 270 C and 320 C. Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards 2004 Oct 04 47 Philips Semiconductors Preliminary specification Analog front end for digital video processors 15.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, VFBGA, XSON DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(5), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L(8), PMFP(9), WQCCN..L(8) Notes not suitable not suitable(4) suitable not not recommended(5)(6) recommended(7) PNX3000 SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable not suitable not suitable 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar soldering or manual soldering is suitable for PMFP packages. 2004 Oct 04 48 Philips Semiconductors Preliminary specification Analog front end for digital video processors 16 DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION PNX3000 This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). II Preliminary data Qualification III Product data Production Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 17 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 18 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2004 Oct 04 49 Philips Semiconductors Preliminary specification Analog front end for digital video processors 19 PURCHASE OF PHILIPS I2C COMPONENTS PNX3000 Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2004 Oct 04 50 Philips Semiconductors - a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. (c) Koninklijke Philips Electronics N.V. 2004 SCA76 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R24/03/pp51 Date of release: 2004 Oct 04 Document order number: 9397 750 14086 |
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